International Journal of Electrical, Electronics and Data Communication (IJEEDC)
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Statistics report
May. 2022
Submitted Papers : 80
Accepted Papers : 10
Rejected Papers : 70
Acc. Perc : 12%
Issue Published : 111
Paper Published : 1546
No. of Authors : 4203
  Journal Paper


Paper Title :
A Novel CNTFET Based Power and Delay Optimized Hybrid Full Adder

Author :Priya Kaushal, Rajesh Mehra

Article Citation :Priya Kaushal ,Rajesh Mehra , (2017 ) " A Novel CNTFET Based Power and Delay Optimized Hybrid Full Adder " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 21-27, Volume-5,Issue-9

Abstract : In this paper, high speed, low power and reduced transistor count full adder cell using CNTFET 32nm technology is presented. Two input full swing XOR gate is design using 4 transistors and then, this is used to generate Sum and Carry output signals. Sum and carry signals are generated by using Gate-Diffusion-Input (GDI) which reduces the number of transistors involved. Proposed design simulated with different voltages (0.8V, 0.9V, 1V) and results are better design as compared to existing circuits in terms of Power, Delay and Power-Delay-Product (PDP). For different operating voltages PDP are 8.6045zJ, 2.004zJ and 4.74aJ respectively for the proposed design. Keywords - Carbon Nanotube Field-Effect Transistor (CNTFET); Nanotechnology; Full Adder; Low Power; High Speed; Power Delay Product.

Type : Research paper

Published : Volume-5,Issue-9


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