Paper Title :Design And Implementation Of Area Optimized Cordic Processor
Author :Arun Mohan
Article Citation :Arun Mohan ,
(2014 ) " Design And Implementation Of Area Optimized Cordic Processor " ,
International Journal of Electrical, Electronics and Data Communication (IJEEDC) ,
pp. 24-28,
Volume-2,Issue-6
Abstract : Abstract- This paper describes the design and implementation in VHDL language of a special purpose processor for the
calculation of trigonometric functions, based on CORDIC (Coordinate rotation in digital computer) algorithm. CORDIC
algorithm implementation has the primary advantage that it is far more economical compared to DSP algorithms in terms of
area and power consumption. This algorithm’s implementation has the edge over conventional DSP methods since it requires
less complex hardware and due to its flexibility. Since CORDIC architecture provides considerable area optimization, it is
ideal for use in Field Programmable Gate Arrays (FPGAs). This property of the CORDIC architecture can be utilized for
reducing the number of components in the FFT (Fast Fourier Transform) part of a processor since we are replacing the
multiplier part of the FFT with the CORDIC processor. The implementation of this FFT part in an OFDM (Orthogonal
Frequency Division Multiplexing) system will eventually result in the reduction of on chip area and hence will lead to more
minimization. Thus this paper explores the idea of implementation of a minimized and efficient OFDM receive transmit
system in FPGA utilizing the advantages provided by the CORDIC algorithm implementation in the FFT module. Thus we
can develop a FPGA system with minimum utilization of CLBs. Modelsim 6.5b is being used for simulation purpose and for
synthesis, Xilinx 14.5 is being used. The CORDIC part is implemented in VHDL using SPARTAN3E XC3S500E.
Type : Research paper
Published : Volume-2,Issue-6
DOIONLINE NO - IJEEDC-IRAJ-DOIONLINE-820
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Published on 2014-06-04 |
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