Paper Title :Design an Efficient Built in Self Test Pattern for Memory Access

Author :P Kranthi, K Madhu Sudhana Rao

Article Citation :P Kranthi ,K Madhu Sudhana Rao , (2017 ) " Design an Efficient Built in Self Test Pattern for Memory Access " , International Journal of Advance Computational Engineering and Networking (IJACEN) , pp. 23-25, Volume-5,Issue-8

Abstract : Built-in self-test repair (BISTR) technique has been most widely used to test repair embedded random access memories (RAMs). This paper proposes a reconfigurable BISTR (ReBISTR) scheme to test repairing RAMs with different sizes and redundancy organizations. An efficient redundancy BIST algorithm is proposed to allocate redundancies of defective RAMs. In the ReBISTR, a reconfigurable built-in self-test and test repair redundancy analysis is (ReBIRA) design circuit is to perform the redundancy algorithm for various RAMs. Also, an adaptive reconfigurable methodology is proposed to reduce the test repair setup time when the RAMs are operated in normal mode. Due to the complexity of memory architectures, the possibility of occurring manufacturing defects is high. Hence memory testing is necessary. Built in Self- Test repair (BISTR) has been proven to be most cost-effective and widely used solutions for memory testing. BISTR technique is used to reduce test repair time. The design architecture is simulated in Xilinx ISE 14.7 tools. Keyterms - RAM [Random access memories], BIST[Built in self test], BISTR[Built in self test repair].

Type : Research paper

Published : Volume-5,Issue-8

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