Paper Title
A Low Leakage Nanoscale CMOS Memory Cell With Virtual Grounding

In this paper we are going to modify the Schmitt Trigger based SRAM for the purpose of more reduced power,leakage & area than the existing type of designs as well as the new design which is combined of virtual grounding with read Error Reduction Logic is compared with the existing technologies & the nanometer technology is also improved for the purpose of much improved reduction of area, leakage & power factors than the Schmitt Trigger based SRAM Designs the simulations were done using microwind & DSCH results