Paper Title :Design Of High Performance 16-Bit Brent Kung Adder Using Static Cmos Logic Style In 45nm Cmos Ncsu Free Pdk
Author :Nirav Desai
Article Citation :Nirav Desai ,
(2014 ) " Design Of High Performance 16-Bit Brent Kung Adder Using Static Cmos Logic Style In 45nm Cmos Ncsu Free Pdk " ,
International Journal of Advances in Science, Engineering and Technology(IJASEAT) ,
pp. 33-35,
Volume-1,Issue-3
Abstract : High performance microprocessor units require high performance adders and other arithmetic units. Modern
microprocessors are however 32-bits or 64-bits as that is the minimum required for floating point arithmetic as per the IEEE
754 Standard. 8-bit and 16-bit arithmetic processors are normally found in micro-controller applications for embedded
systems where high speed is important but low power constraints dominate system design. A good metric of performance on
such designs would be the power-delay product (or equivalently energy per bit.) Many designs give a high speed at the cost
of more power or low power at the cost of low speed. The design of a 16-bit Brent Kung adder presented here has the lowest
delay (among the adders compared, Table 2) and also the lowest power-delay product (among the adders compared, Table 2)
in similar technology nodes. The design makes use of logical effort
[2]
based sizing of transistors and advanced layout
techniques like fingering and inter-digitating to reduce the self-loading of the transistors from parasitic transistor
capacitances.
Type : Research paper
Published : Volume-1,Issue-3
DOIONLINE NO - IJASEAT-IRAJ-DOIONLINE-328
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Copyright: © Institute of Research and Journals
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Published on 2014-01-22 |
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