International Journal of Electrical, Electronics and Data Communication (IJEEDC)
eISSN:2320-2084 , pISSN:2321-2950
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Jul. 2024
Submitted Papers : 80
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  Journal Paper

Paper Title :
Structural Modeling Of Intelligent Traffic Light Controller On FPGA

Author :Surabhi S. Gaopande, Ashwini D. Bharade

Article Citation :Surabhi S. Gaopande ,Ashwini D. Bharade , (2014 ) " Structural Modeling Of Intelligent Traffic Light Controller On FPGA " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 63-66, Volume-2,Issue-9

Abstract : The paper presents an adaptive traffic light controller customized to have user defined number of intersection lanes and counts of signals for various intersections. Conventional traffic systems can be installed for a non-dynamic number of intersections with fixed counts of signal durations and are typically microcontroller based. The proposed system prototype is implemented on FPGA which offers many advantages over microcontrollers such as fast speed, number of input/output ports and enhanced performance coupled with low cost than ASIC design. Typical TLCs are modeled using the finite state paradigm and rely heavily on software design flow. In this paper, the hardware design has been deployed using the structural style of VHDL programming and thus offers more robustness. The system has been successfully tested and implemented in hardware using Xilinx Cyclone III: EP3C10F256C6. The efficient design thus offers a dynamic way that allows the user to design a robust TLC and thus it breaks through the bottleneck of traditional traffic signal controller, and can accomplish the control in complicated and diversified traffic.

Type : Research paper

Published : Volume-2,Issue-9


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