International Journal of Electrical, Electronics and Data Communication (IJEEDC)
eISSN:2320-2084 , pISSN:2321-2950
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Statistics report
Jul. 2024
Submitted Papers : 80
Accepted Papers : 10
Rejected Papers : 70
Acc. Perc : 12%
Issue Published : 136
Paper Published : 1737
No. of Authors : 4816
  Journal Paper

Paper Title :
Analog Layout Generation Based on EMIR Optimization

Author :Alaa Hassan, Chaymaa Osama, Sameh Ibrahim

Article Citation :Alaa Hassan ,Chaymaa Osama ,Sameh Ibrahim , (2024 ) " Analog Layout Generation Based on EMIR Optimization " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 42-47, Volume-12,Issue-1

Abstract : Analog Layout Automation is an emerging area of current research that addresses an important issue in the field. Designing analog layouts is time-consuming due to their complex- ity and the need for precise performance. The goal of automating this process is to speed up layout creation while also ensuring important conditions are met, like optimizing performance and following Electromigration and IR drop (EMIR) rules. In light of these imperatives, this paper introduces an inno- vative workflow that revolutionizes the entirety of the design process. The central objective of this novel approach is to significantly expedite the design process by enabling the creation of layouts at an accelerated pace, while meticulously upholding the intricacies of EMIR regulations. Keywords - Layout Automation, EMIR, SKILL, OTA

Type : Research paper

Published : Volume-12,Issue-1


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