International Journal of Electrical, Electronics and Data Communication (IJEEDC)
eISSN:2320-2084 , pISSN:2321-2950
Follow Us On :
current issue
Volume-12,Issue-4  ( Apr, 2024 )
  1. Volume-12,Issue-3  ( Mar, 2024 )
  2. Volume-12,Issue-2  ( Feb, 2024 )
  3. Volume-12,Issue-1  ( Jan, 2024 )

Statistics report
Jul. 2024
Submitted Papers : 80
Accepted Papers : 10
Rejected Papers : 70
Acc. Perc : 12%
Issue Published : 136
Paper Published : 1737
No. of Authors : 4816
  Journal Paper

Paper Title :
Low Power Digital ADC Architecture Using Reversible Logic Gatesin 65nm Technology

Author :Naveen K B, M N Sree Rangaraju

Article Citation :Naveen K B ,M N Sree Rangaraju , (2016 ) " Low Power Digital ADC Architecture Using Reversible Logic Gatesin 65nm Technology " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 104-109, Volume-4,Issue-10

Abstract : In the deep submicron CMOS technology, the planning of analog and complicated mixed could be a huge challenge. Therefore it's fascinating to shift converter from analog domain to the digital domain. The benefits of implementing a completely digital ADC style rather than ancient analog ADC style are that it's easy to design and implement. It offers low power consumption, smaller space and a completely optimized gate-level circuit that reduces the planning prices. The functioning of all-digital ADC relies on the time domain signal process approach, which brings time resolution obtained by the employment of CMOS technology. Digital ADC style is enforced by employing combination of the digital Voltage-Controlled generator and a Time-to-Digital device. The VCO converts the amplitude-domain analog signal to a phase-domain time-based signal. The time-based signal from the VCO output is then processed by the TDC quantizer so as to come up with the digital code sequences. Power is reducing by applying reversible logic concept to the digital ADC architecture. This paper presents the implementation of a VCO-based digital ADC in TSMC 65nm CMOS technology victimization digital tools like ModelSim simulator and Cadence RTL Compiler. A multi-phase VCO and multibit quantization design has been chosen for this 8-bit ADC. Keywords- Low Power, Digital ADC, Verilog HDL Coding, VCO Based ADC, Reversible Logic Gates

Type : Research paper

Published : Volume-4,Issue-10


Copyright: © Institute of Research and Journals

| PDF |
Viewed - 79
| Published on 2016-11-30
IRAJ Other Journals
IJEEDC updates
Volume-12,Issue-4(April ,2024) Want to join us ? CLick here
The Conference World



Technical Editor, IJEEDC
Department of Journal and Publication
Plot no. 30, Dharma Vihar,
Khandagiri, Bhubaneswar, Odisha, India, 751030
Mob/Whatsapp: +91-9040435740